The China International 'Internet+' College Student Innovation and Entrepreneurship Competition, jointly organized by the Ministry of Education, universities, and enterprises, aims to deepen comprehensive reforms in higher education. It seeks to ignite students' creativity and nurture the backbone of 'mass entrepreneurship and innovation.' SOPHGO, as a collaborative partner, has provided six competition themes based on TPU processors and RISC-V processors, along with corresponding computational hardware support, attracting numerous student teams from various universities to register and participate.

For this entrepreneurial competition, SOPHGO provides the following six competition themes:

1. Face recognition access control system based on domestically produced TPU processors.
2. Depth estimation using domestically produced TPU processors.
3. Surround-view fusion based on domestically produced TPU processors.
4. Embedded deep learning desktop voice assistant based on domestically produced RISC-V architecture processors.
5. Disaster relief lighting drones using domestically produced RISC-V architecture processors.
6. Intelligent innovative applications targeting domestically produced high-performance RISC-V architecture processors.

 

Topic 1: Face Recognition Access Control System Based on Domestic TPU Processor Proposition

 

• Background:

With the rapid development of deep learning technology and the comprehensive promotion of 5G networks, face recognition access control systems have been widely used in various fields of social production and life. However, existing face recognition access products in the market predominantly use foreign processors and algorithms, making them relatively expensive and posing certain security risks. Therefore, researching and developing a face recognition access control system based on domestic TPU processors has become particularly important.

 

Simultaneously, since face recognition access control systems involve critical issues such as personal privacy and security, it is imperative to fully consider data protection and safety concerns. Moreover, to meet the needs of different industries and scenarios, the face recognition access control system needs to possess characteristics such as high accuracy, efficiency, user-friendliness, as well as good scalability and maintainability to adapt to future development requirements.

 

The objective of this competition is to provide new ideas and solutions for the development of face recognition access control systems based on domestic TPU processors through the innovation and efforts of participating contestants. This aims to drive innovation and application of related technologies.

 

• Proposition Content

1. Select the SOPHON Shaolin board as the main development board.
2. The system needs to accomplish the following functions:

1）Face Detection and Recognition: Capture facial images through a camera and employ the BM1684 processor to detect and recognize faces.

2）Access Control: Control the opening and closing of access points through a controller, allowing or denying entry of individuals.

3）Data Storage and Management: Store personnel information and entry/exit records in a database, providing an interface for administrators to view and query this data.

4）System Security: Ensure the system's security to prevent unauthorized access by individuals.

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Topic 2: Depth Estimation Based on Domestic TPU Processor Proposition

 

• Background

In recent years, with the rapid development of computer vision and technologies like autonomous driving, depth estimation has found wide applications in fields like image processing, object detection, and 3D structure reconstruction. Depth estimation essentially computes the depth value of each pixel from the camera, allowing for the inference of three-dimensional structure and object positions in a scene. The accuracy and efficiency of depth estimation are crucial for the realization of related applications.

 

Traditional depth estimation methods primarily rely on processors or graphics for calculations, but due to high computational requirements and long processing times, their efficiency is limited. With the advent of deep learning processors, especially the gradual maturity of domestic TPU processors, attention and application toward depth estimation based on TPU processors are increasing. Implementing depth estimation based on domestic TPU processors can enhance system performance and reduce costs, signifying its importance.

 

The objective of this competition is to provide new ideas and solutions for depth estimation based on domestic TPU processors through innovation and effort from participants. This aims to drive innovation and application of related technologies.

 

• Proposition Content

1. Select the SOPHON Shaolin board as the main development board.

2. The system must achieve the following functions:

   a) Depth image generation: Input RGB images and output depth information for each pixel.

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Topic 3: Omnidirectional Fusion Based on Domestic TPU Processor Proposition

 

• Background

With the rapid development of intelligent mobile terminals and computer vision technology, omnidirectional fusion has become a popular field, widely applied in areas such as automotive, robotics, and security. Omnidirectional fusion involves merging images captured by multiple cameras to achieve comprehensive environmental perception and object detection.

 

Traditional omnidirectional fusion usually requires high computational and storage resources. However, omnidirectional fusion based on domestic TPU processors offers higher efficiency and lower costs. TPU processors, with advantages like low power consumption, high performance, low latency, and ease of integration, have been extensively applied in omnidirectional fusion systems. They can enhance computing speed, parallel processing capabilities, reduce costs, and energy consumption, which is crucial.

 

The goal of this competition is to provide new ideas and solutions for omnidirectional fusion based on domestic TPU processors through innovation and effort from participants, promoting innovation and application of relevant technologies, thereby supporting the development of intelligent transportation, robotic navigation, virtual reality, and other fields.

 

• Proposition Content

1. Select the SOPHON Shaolin board as the main development board.
2. The system needs to achieve the following functions:

a) Multi-camera capture: Use multiple cameras to capture the surrounding environment and transmit the collected data to the main controller.

b) Video stream synchronization: Synchronize video streams based on timestamps from each camera to ensure consistency and temporal ordering.

c) Image registration: Register and correct images captured by different cameras to eliminate distortions and deviations caused by camera positions and angles.

d) Omnidirectional fusion: Merge registered images to generate panoramic images or videos.

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Topic 4: Embedded Deep Learning Desktop Voice Assistant Based on Domestic RISC-V Architecture Processor

 

• Background

In recent years, the rapid advancement of deep learning technology has brought significant convenience and transformative changes to our daily lives. Embedded artificial intelligence technology, as a crucial branch of deep learning, holds vast application prospects in smart homes, intelligent transportation, and healthcare fields.

 

Within the embedded deep learning domain, voice assistants stand as a pivotal technology. These assistants interact with users through speech recognition, natural language processing, and speech synthesis, providing services based on user demands. Currently, several renowned voice assistant products like Siri, Alexa, and Google Assistant have found widespread usage in smartphones, smart speakers, and other devices.

 

However, existing voice assistants primarily rely on traditional computing platforms and processor architectures. To foster the development of the country's information technology industry, bolster independent innovation capabilities, domestic enterprises, and research institutions have embarked on developing embedded deep learning voice assistants based on domestic RISC-V architecture processors. The RISC-V architecture, an open-source instruction set architecture, with its flexibility, scalability, and customizability, is deemed a crucial technical backbone for the future of embedded deep learning.

 

Therefore, aiming to stimulate research and development of embedded deep learning desktop voice assistants based on domestic RISC-V architecture processors, this competition topic has been specially crafted. Participants will have the opportunity to delve deeper into the characteristics and advantages of RISC-V architecture, explore the development and application of embedded deep learning voice assistants in practice, and enhance their understanding and application capabilities of technologies like speech recognition and natural language processing. Moreover, this research will actively contribute to propelling independent innovation in the country's information technology industry, nurturing high-level innovative talents in the field of deep learning, and making constructive contributions.

 

• Proposition Content

1. Select the Milk-V Duo development board from Shenzhen Qunxin Shanyao Technology Co., Ltd.

2. At a minimum, the system should achieve the following functionalities:

   a) Voice input for queries

   b) Retrieval of answers to queries through a natural language model (leveraging existing model APIs is an effective approach)

   c) Interaction with users via any format (could be displayed on a screen or used as an external device to control other devices)

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Topic 5: Disaster Relief Illumination UAV Based on Domestic RISC-V Architecture Processor

 

• Background

Recently, Turkey experienced a severe earthquake causing significant destruction and casualties. In this catastrophe, domestically developed disaster relief illumination UAVs showcased their significance and application value. Disaster relief illumination UAVs, through their inbuilt lighting apparatus, can provide extensive, high-intensity, and enduring lighting in disaster zones. This is critical for nighttime rescue operations and post-disaster reconstruction, aiding in enhancing rescue efficiency, ensuring safety, and providing necessary light sources and hope to affected populations.

 

Disaster relief illumination UAVs possess several advantages. Their lightweight design facilitates easy transport of UAVs, enabling rapid responses in complex disaster environments. Additionally, their efficient energy utilization and intelligent control systems allow these UAVs to offer uninterrupted lighting support in disaster zones for extended periods, providing sustained capability for rescue operations.

 

This competition aims to encourage participants to further advance the technology of disaster relief illumination UAVs based on domestic RISC-V architecture processors through innovation and effort. Participants will have the opportunity to gain in-depth understanding of the characteristics and advantages of RISC-V architecture, explore the application of embedded systems and deep learning technology in the field of disaster relief illumination UAVs. Simultaneously, this research will contribute positively to independent innovation in the country's information technology industry, cultivate high-level innovative talents in the fields of embedded systems and deep learning, and contribute to enhancing disaster relief efficiency and ensuring the safety of affected populations.

 

• Proposition Content

1. Select the Milk-V Duo development board from Shenzhen Qunxin Shanyao Technology Co., Ltd.

2. It can be a single-axis or multi-axis (3-axis, 4-axis, etc.) UAV.

3. At a minimum, the system should achieve the following functionalities:

   a) Stability at a certain height, hovering for 10 seconds (some jitter is permissible)

   b) Ability to illuminate a specific area on the ground from above (for demonstration purposes only)

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Topic 6: Intelligent Innovative Applications for Domestic High-Performance RISC-V Architecture Processors

 

• Background

When surveying the global landscape of processor instruction sets, there are primarily ARM, X86, and RISC-V architectures. RISC-V stands out as a fully open instruction set architecture that can be freely used by any academic institution or commercial organization, serving as a genuinely suitable and stable standard instruction set for hardware implementation. On March 2, 2023, Alunar released the industry's first server-grade RISC-V processor, the SG2042, propelling RISC-V towards high-performance computing. This processor is based on a high-performance RISC-V core, featuring a 9-12 pipeline design, supporting out-of-order execution, boasting a clock speed of up to 2GHz, allowing up to 4 cores per cluster, and a single SoC processor possessing 64 cores and a shared 64MB level 3 cache, catering to various data center needs.

 

However, the software ecosystem for RISC-V servers is relatively limited. Besides Linux kernel-based operating system distributions like Ubuntu, OpenEuler, there's limited stable support for fundamental open-source software like Java runtime environments, Python interpreters, MySQL databases, Tomcat middleware, etc. Furthermore, there's a scarcity of typical applications geared towards hot fields like deep learning and big data analysis. Thus, there's an urgent need to collaborate domestically and internationally to overcome these challenges.

 

Hence, through this proposition, it aims to leverage the imagination and initiative of participating teams, combining RISC-V, TPU, deep learning, and other trending technologies. This initiative aims to showcase the team's vitality, capability, and creativity through innovative applications and drive the development of the RISC-V software ecosystem.

 

• Proposition Content

Based on the Milk-V Pioneer or other boards integrated with SG2042 available in the market, adapt market-leading deep learning graphics or TPUs like SOPHON BM1684X, capable of supporting large-scale inference computations. With this, design and implement intelligent innovative applications geared towards popular deep learning application scenarios such as natural language processing, facial recognition, and structured video processing, specifically tailored for domestic high-performance RISC-V architecture processors.

 

Competition Registration

The sole official registration platform for this competition: National College Students' Entrepreneurship Service Website (https://cy.ncss.cn/mtcontest/index).

• Registration (May to August 2023)

Teams can register at the National College Students Entrepreneurship Service Network (https://cy.ncss.cn). Check the 'Download' section for a registration guide. Contact via WeChat at 'National College Students Entrepreneurship Service Network' for event inquiries. Judging rules will be announced soon. Registration starts on May 29, closing dates vary per region but not later than August 15, 2023. International participants register at www.pilcchina.org.

 

• Preliminary and Semi-Final Rounds (June to August 2023)

Log in at https://cy.ncss.cn/gl/login for competition management. Regions should complete provincial semi-finals by August 31. Finalist selection announced by then.

 

• Final Competition (September to October 2023)

Gold, silver, and bronze awards. Projects undergo evaluations for on-site finals. Services provided via National College Students Entrepreneurship Service Network and https://www.ncss.cn.

1. The competition adopts a three-tiered system: university-level preliminaries, provincial-level semifinals, and a final. This excludes the budding track and international projects. University-level preliminaries are organized by respective institutions, while provincial semifinals are managed by local authorities. The final selection for the ultimate round is based on quotas determined by the organizing committee, considering factors such as the number of participating teams (including invited international projects), participating institutions, and the state of innovation and entrepreneurship education.
2. A total of 4,100 projects will enter the final competition (with separate quotas for Hong Kong, Macau, and Taiwan), including 400 projects in the industry-sponsored track.
3. Each institution can nominate up to three projects per proposition in the industry-sponsored track.
4. Students currently enrolled or graduated within 5 years from vocational schools, technical colleges, vocational education undergraduates, regular undergraduates, master's and doctoral students, and students from open universities are eligible to participate. However, each track and its subgroups have varying requirements regarding the academic qualifications of participants. Applicants should register for the competition according to the specific academic requirements for different tracks and subgroups.